The present invention relates to a semiconductor integrated circuit device, and more specifically to a semiconductor integrated circuit device provided with an input-protecting circuit.
FIG. 4 is a circuit diagram showing both an input-protecting circuit related to the present invention and a first stage of an internal circuit. In FIG. 4, an input terminal 101 for inputting an external signal is connected to an inverter INV11 at a node N11. The inverter INV11 is a first stage of an internal circuit and composed of a P-channel transistor 103 and an N-channel transistor 104. Further, an N-channel transistor 102 is connected to the node N11 as an input protecting circuit. In more detail, the source of this N-channel transistor 102 is connected to the node N11, and the gate and drain thereof are both grounded. Further, a substrate bias voltage is supplied from a substrate bias circuit (not shown) to a substrate terminal of the N-channel transistors 102 and 104. Further, although not shown, a succeeding stage (not shown) of the internal circuit is connected to an output terminal 105 of the inverter INV11.
FIG. 5 shows a longitudinal cross-sectional view of a semiconductor substrate on which the above-mentioned input-protecting N-channel transistor 102 and the inverter INV11 are both formed.
A p-type semiconductor substrate 111 is formed with a source region (n.sup.+ -type impurity region) 114, a drain region (n.sup.+ -type impurity region) 113, a gate oxide film 125, and a gate electrode 126, so as to construct the N-channel transistor 102.
Further, the p-type semiconductor substrate 111 is formed with a source region (n.sup.+ -type impurity region) 115, a drain region (n.sup.+ -type impurity region) 116, a gate oxide film 127, and a gate electrode 128, so as to construct the N-channel transistor 104 of the inverter INV11. Further, the substrate 111 is formed, in an n type well 117, with a source region (p.sup.+ -type impurity region) 121, a drain region (p.sup.+ -type impurity region) 118, a gate oxide film 119, and a gate electrode 120, so as to construct the P-channel transistor 103 of the inverter INV11. In this n-type well 117, an n.sup.+ -impurity region 122 is further formed so as to be connected to a supply voltage (Vcc) terminal V.sub.CC. Further, the two drain regions 116 and 118 are connected to an output terminal 105.
In the circuit as described above, when a negative surge voltage is applied to the input terminal 101, in the input-protecting N-channel transistor 102, current flows from the ground terminal V.sub.SS to the input terminal 101 only when a potential difference between the source region 114, connected to the input terminal 101, and the drain region 113 and the gate electrode 126, both connected to the ground terminal V.sub.SS, exceeds a threshold voltage of the N-channel transistor 102. Therefore, it is possible to prevent a negative surge voltage from being applied to the inverter INV11, that is, the first input stage of the internal circuit, with the result that the internal circuit can be protected from the surge voltage applied to the input terminal.
Here, the dielectric strength of the gate oxide films 119 and 127 of the inverter INV11 against the negative surge voltage is determined on the basis of the current characteristics of the N-channel transistor 102 which serves as an input-protecting circuit. Accordingly, when the current-driving capability of the N-channel transistor 102 is increased, it is possible to improve the input-protection characteristics. In this case, however, when the width W of the N-channel transistor 102 is increased to obtain a high current-driving capability, since it is necessary to suppress an increase of the input capacitance, there exists inevitably a restriction in an increase of the width W. On the other hand, when the length L of the N-channel transistor 102 is shortened, the dielectric breakdown of the input-protecting N-channel transistor 102 itself deteriorates, with the result that it is impossible to increase the breakdown voltage of the input-protecting transistor 102 against a surge voltage.
For the reasons as above, in the input-protecting circuit as shown in FIG. 5, it has been so far difficult to improve the input-protecting characteristics sufficiently.